STX Electrical – Flat Panel Interface
 
The STX Interface supports two modes of digital flat panel interface – 24-bit and 12-bit. It allows to use the different types of graphics controllers on the STX Module. STX flat panel interface is compatible with the Silicon Image's SiI154 and SiI164 PanelLink transmitters that can be used to drive the flat panels with TMDS interface.

Flat panel interface mode in use is indicated by FP_BSEL signal. The pixel data mapping in both 24-bit and 12-bit modes is described in the following table.

Flat Panel Pixel Data Mapping

Flat Panel
Data Signal
24-bit Mode
(Pixel Data)
12-bit Mode
(Low/High Half of Pixel Data)
FP_D23R7
FP_D22R6
FP_D21R5
FP_D20R4
FP_D19R3
FP_D18R2
FP_D17R1
FP_D16R0
FP_D15G7
FP_D14G6
FP_D13G5
FP_D12G4
FP_D11G3G3/R7
FP_D10G2G2/R6
FP_D9G1G1/R5
FP_D8G0G0/R4
FP_D7B7B7/R3
FP_D6B6B6/R2
FP_D5B5B5/R1
FP_D4B4B4/R0
FP_D3B3B3/G7
FP_D2B2B2/G6
FP_D1B1B1/G5
FP_D0B0B0/G4

Additional Info
R, G, B denotes red, green, and blue color pixel components. Bit significance within a color is defined by number (7 denotes MSB). When modes with color depth less than 8 bit is used, LSB pixel bits are driven low.

The FP_DSEL signal defines single or dual clock mode used in 12-bit mode. The FP_EDGE selects an active edge of the clock signal. See following tables for definition of the clock edge used for pixel data sampling in different modes.

Sampling Edge in 24-bit Mode (FP_BSEL=1)

FP_DSELFP_EDGE24-bit Pixel Data
00FP_CLK_P falling edge
01FP_CLK_P rising edge
10
11

 

Sampling Edge in 12-bit Mode (FP_BSEL=0)

FP_DSELFP_EDGELow Half of Pixel DataHigh Half of Pixel Data
00FP_CLK_P falling edgeFP_CLK_S falling edge
01FP_CLK_P rising edgeFP_CLK_S rising edge
10FP_CLK_P falling edgeFP_CLK_P rising edge
11FP_CLK_P rising edgeFP_CLK_P falling edge
 


Updated 01/Nov/2001