STX Electrical – PCI Bus
 
The STX interface supports up to three external PCI devices with bus master capability. Additionally the fourth PCI device without bus master support can be connected provided that clock signal is replicated.

Clock Distribution

The STX Module provides clock signals for three external PCI devices or slots on the STX Baseboard. The maximum skew of 2 ns shall be maintained across the system operating at 33 MHz between any two PCI devices at the clock input of the integrated circuits.

There are two components that contribute to clock skew in a STX system:

  • STX Module clock skew
  • STX Baseboard clock skew

The STX Module clock distribution circuitry has to be designed to accomodate the STX Baseboard skew. The clock distribution circuitry provides a discrete clock signal to each of the STX connector pins defined as PCI clock (CLK[2..0]). The routing of these signals shall be matched in length. Any on-board STX device shall be provided a clock that is delayed to accomodate the maximum propagation delay of the baseboard clocks and still meet the 2 ns overall skew requirement.

Clock Signal Lenght

Each external PCI device on STX Baseboard shall be provided a discrete clock signal. The clock signals on the STX Baseboard has to be designed with a delay of 800 ps between STX connector clock pins and PCI device clock input pins. As the typical trace velocity is in the range of 60–75 ps/cm, the trace length of the clock signals should be 10–14 cm.

The fourth PCI device can be connected provided that clock signal is replicated. The zero-delay buffer based on PLL technology must be used in this case to maintain the overall maximum skew.

IDSEL Mapping

To avoid possibility of contention between selecting PCI devices on the STX Baseboard and PCI devices on the STX Module, AD[23..20] lines are used to support IDSEL signals on the STX Baseboard devices as can be seen in table PCI Interrupt Routing. This mapping is compatible with PC-104+ specification.

Expansion connectors and devices connected directly to STX connectors are considered to be on bus 0.

Interrupt Routing

To standardize the interrupt assignation in the system BIOS and OS, the interrupt binding scheme is defined in the following table. Used interrupt routing is compatible with PC-104+ specification.
 

PCI Interrupt Routing

IDSEL
Mapping		STX Interrupt Signal
INTA#INTB#INTC#INTD#
AD20INTA#INTB#INTC#INTD#
AD21INTD#INTA#INTB#INTC#
AD22INTC#INTD#INTA#INTB#
AD23INTB#INTC#INTD#INTA#

Signaling Voltage Level

The STX Module can use 5V or 3.3V PCI signaling level. To allow design of universal STX Baseboard with PCI devices supporting the both signaling levels, the V_IO pin is defined on the STX Interface. This pin is conected to VCC when 5V signaling level is used and to VCC3 in 3.3V environment. V_IO can be used for PCI I/O buffer power supply and maximal current drawn from this pin must not exceed 250mA. There is no mechanical keying system defined for STX Module to specify whether the STX Module uses 5V or 3.3V signaling level.

Note
STX Module requires both 5V and 3.3V power supply irrespective of used PCI signaling level.
 

Updated 01/Nov/2001